1. Technical Field
This patent relates to a semiconductor device, and more particularly to a multi-word line refresh-type semiconductor device for performing a refresh operation simultaneously with respect to a plurality of word lines for each bank in a self-refresh mode.
2. Description of the Related Art
With the advance of wireless communications and the development of various contents, a matter of reduction in power consumption of mobile products has become a very important issue. In this regard, a matter of reduction in refresh current has become one important issue in dynamic random access memories (DRAMs). The refresh operation of a semiconductor device, such as a DRAM, is classified into an auto-refresh type and a self-refresh type. In the refresh operation, the semiconductor device refreshes each word line of a memory core at a certain period appropriate to a refresh retention time of each cell in the memory core according to a given operation type.
A self-refresh mode is an operation mode where, when a system including the DRAM is not operated for a certain time, the DRAM performs the refresh operation by itself for retention of information stored therein. It is therefore preferable that a smaller amount of current is consumed in the self-refresh mode.
Conventionally, the refresh operation is performed with respect to one word line for each bank in the DRAM in the self-refresh mode. Accordingly, whenever the refresh operation is performed, a series of control circuits are operated to activate a corresponding word line and a sense amplifier which drives that word line. For this reason, assuming that 8×1024 word lines are present in each bank, the series of control circuits must be operated 8×1024 times to refresh data in cells connected to all those word lines, resulting in a large amount of operating current being consumed.
In order to solve the above problem, a multi-word line refresh-type semiconductor device has been proposed in which an increased number of word lines, namely, two or more word lines, not one word line, are activated in one refresh operation. That is, in one refresh operation, at least two word lines are refreshed for each bank. As a result, in the proposed semiconductor device, the refresh rate is increased to at least twice that in the above-mentioned method. However, this multi-word line refresh-type semiconductor device has a problem as will be described below.
FIG. 1 is a block diagram showing the configuration of a conventional multi-word line refresh-type semiconductor device, which is an exemplary semiconductor device for performing a refresh operation simultaneously with respect to two word lines for each bank in a self-refresh mode.
As shown in FIG. 1, in the conventional semiconductor device, one bank is partitioned into an upper block and a lower block, and a row controller 121 and a row controller 122 are separately installed to control the refresh operation with respect to the upper block and lower block, respectively. An upper fuse circuit 111 and a lower fuse circuit 112 are separately installed to receive a refresh address xadd, determine whether the received refresh address xadd corresponds to a word line to be repaired (i.e., a failed word line to be replaced with a redundancy word line), and output a redundancy word line enable signal red_en_h and a redundancy word line enable signal red_en_l according to a result of the determination, respectively.
In the conventional semiconductor device, as shown in FIG. 1, in the self-refresh mode, two word lines whose bit values of the refresh address xadd, except a bit value for block selection (for example, a most significant bit (MSB) value), are the same are selected one by one respectively in the upper block 131 and lower block 132, and the refresh operation is performed simultaneously with respect to the selected two word lines. For example, the refresh operation is performed simultaneously with respect to a word line SWL00_h and a word line SWL00_l. This refresh operation is performed sequentially with respect to up to a word line SWLx_h and a word line SWLx_l. On the other hand, in the case where the refresh address xadd corresponds to a word line to be repaired which is a failed word line to be replaced with a redundancy word line, the upper fuse circuit 111 or lower fuse circuit 112 determines the refresh address xadd to correspond to the word line to be repaired, and then outputs the control signal red_en_h or control signal red_en_l to replace the word line to be repaired with the redundancy word line. Then, the row controller 121 or row controller 122 performs the refresh operation with respect to the redundancy word line in response to the control signal red_en_h or control signal red_en_l. As a result, in this case, redundancy word lines installed respectively in the upper block and lower block in one bank are used for only the corresponding blocks. In other words, the conventional dual word line refresh scheme requires redundancy word lines which are twice as many as those in a single word line refresh scheme which performs the refresh operation with respect to only one word line. For this reason, the conventional semiconductor device has a disadvantage in that the number of redundancy word lines is increased, resulting in an increase in chip area. It is also disadvantageous in that repair efficiency of each redundancy word line is reduced.